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HM62256B Series
32,768-word x 8-bit High Speed CMOS Static RAM
ADE-203-135D (Z) Rev. 4.0 Nov. 29, 1995 Description
The Hitachi HM62256B is a CMOS static RAM organized 32-kword x 8-bit. It realizes higher performance and low power consumption by employing 0.8 m Hi-CMOS process technology. The device, packaged in 8 x 14 mm TSOP, 8 x 13.4 mm TSOP with thickness of 1.2 mm, 450-mil SOP (foot print pitch width), 600-mil plastic DIP, or 300-mil plastic DIP, is available for high density mounting. It offers low power standby power dissipation; therefore, it is suitable for battery back-up systems.
Features
* High speed Fast access time: 45/55/70/85 ns (max) * Low power Standby: 1.0 W (typ) Operation: 25 mW (typ) (f = 1 MHz) * Single 5 V supply * Completely static memory No clock or timing strobe required * Equal access and cycle times * Common data input and output Three state output * Directly TTL compatible All inputs and outputs * Capability of battery back up operation
HM62256B Series
Ordering Information
Type No. HM62256BLP-7 HM62256BLP-7SL HM62256BLSP-7 HM62256BLSP-7SL HM62256BLFP-7T HM62256BLFP-4SLT HM62256BLFP-5SLT HM62256BLFP-7SLT
*1
Access Time Package 70 ns 70 ns 70 ns 70 ns 70 ns 45 ns 55 ns 70 ns 70 ns 85 ns 70 ns 85 ns
*1
600-mil 28-pin plastic DIP (DP-28)
300-mil 28-pin plastic DIP (DP-28NA)
450-mil 28-pin plastic SOP (FP-28DA)
HM62256BLFP-7ULT HM62256BLT-8 HM62256BLT-7SL HM62256BLTM-8 HM62256BLTM-4SL HM62256BLTM-5SL HM62256BLTM-7SL
8 mm x 14 mm 32-pin TSOP (TFP-32DA) 8 mm x 13.4 mm 28-pin TSOP (TFP-28DA)
45 ns 55 ns 70 ns 70 ns
HM62256BLTM-7UL Note:
1. Under development
2
HM62256B Series
Pin Arrangement
HM62256BLP/BLFP/BLSP Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
HM62256BLT Series OE A11 NC A9 A8 A13 WE VCC A14 A12 A7 A6 A5 NC A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) HM62256BLTM Series 22 23 24 25 26 27 28 1 2 3 4 5 6 7 (Top View) 21 20 19 18 17 16 15 14 13 12 11 10 9 8
A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 V SS I/O2 I/O1 I/O0 A0 A1 A2
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A10 CS NC I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 NC A1 A2
Pin Description
Symbol A0 - A14 I/O0 - I/O7 CS WE OE NC VCC VSS Function Address Input/output Chip select Write enable Output enable No connection Power supply Ground
3
HM62256B Series
Block Diagram
V CC V SS
* * * * * * * *
(MSB) A12 A5 A7 A6 A8 A13 A14 A4 (LSB) A3 Memory Matrix 512 x 512
Row Decoder
* *
I/O0
* * * * *
* * * * * * *
Column I/O Column Decoder
* *
Input Data Control
* * *
I/O7
(LSB)
A2 A1 A0 A10 A9 A11
* *
(MSB)
* *
CS WE OE
Timing Pulse Generator Read/Write Control
Function Table
WE X H H L L Note: CS H L L L L OE X H L H L Mode Not selected Output disable Read Write Write VCC Current I SB , I SB1 I CC I CC I CC I CC I/O Pin High-Z High-Z Dout Din Din Ref. Cycle -- -- Read cycle (1)-(3) Write cycle (1) Write cycle (2)
X: H or L
4
HM62256B Series
Absolute Maximum Ratings
Parameter Power supply voltage Terminal voltage
*1 *1
Symbol VCC VT PT Topr Tstg Tbias
Value -0.5 to +7.0 -0.5* to VCC + 0.3 1.0 0 to + 70 -55 to +125 -10 to +85
2 *3
Unit V V W C C C
Power dissipation Operating temperature Storage temperature Storage temperature under bias
Notes: 1. Relative to VSS 2. VT min: -3.0 V for pulse half-width 50 ns 3. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 -0.5
*1
Typ 5.0 0 -- --
Max 5.5 0 VCC+0.3 0.8
Unit V V V V
1. VIL min: -3.0 V for pulse half-width 50 ns
5
HM62256B Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
Parameter Input leakage current Output leakage current Operating power supply current Symbol Min Typ*1 Max Unit Test Conditions |ILI| |ILO | I CC -- -- -- -- -- -- 6 -- 1 1 15 70 A A mA mA Vin = VSS to V CC CS = VIH or OE = VIH or WE = VIL, VSS VI/O VCC CS = VIL, others = VIH/VIL I I/O = 0 mA min cycle, duty = 100 %, II/O = 0 mA CS = VIL, others = VIH/VIL
Average operating HM62256B-4 I CC1 power supply current HM62256B-5 I CC1 HM62256B-7 I CC1 HM62256B-8 I CC1 I CC2 Standby power supply current I SB I SB1
-- -- -- -- -- -- --
-- 33 29 5 0.3 0.2 0.2 0.2
*2 *3
60 60 50 15 2 100 50
*2
mA mA A
Cycle time = 1 s, II/O = 0 mA CS = VIL, V IH = VCC, VIL = 0 CS = VIH Vin 0 V, CS V CC - 0.2 V,
10*3 0.4 -- V V I OL = 2.1 mA I OH = -1.0 mA
Output low voltage Output high voltage
VOL VOH
--
--
2.4 --
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. This characteristics is guaranteed only for L-SL version. 3. This characteristics is guaranteed only for L-UL version.
Capacitance (Ta = 25C, f = 1.0 MHz)*1
Parameter Input capacitance
*1 *1
Symbol Cin CI/O
Min -- --
Typ -- --
Max 8 10
Unit pF pF
Test Conditions Vin = 0 V VI/O = 0 V
Input/output capacitance Note:
1. This parameter is sampled and not 100% tested.
6
HM62256B Series
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: 0.8 V to 2.4 V Input rise and fall times: 5 ns Input and output timing reference level: 1.5 V Output load: HM62256B-4: 1 TTL Gate + CL (30 pF)(Including scope & jig) HM62256B-5: 1 TTL Gate + CL (50 pF)(Including scope & jig) HM62256B-7/8: 1 TTL Gate + C L (100 pF)(Including scope & jig)
Read Cycle
HM62256B -4 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Chip selection to output in low-Z Output enable to output in low-Z Chip deselection in to output in high-Z Output disable to output in high-Z Output hold from address change Symbol t RC t AA t ACS t OE t CLZ t OLZ t CHZ t OHZ t OH 5 5 0 0 5 -5 -7 -8 Notes
Min Max Min Max Min Max Min Max Unit 45 -- -- -- 45 45 30 -- -- 20 20 -- 55 -- -- -- 5 5 0 0 5 -- 55 55 35 -- -- 20 20 -- 70 -- -- -- 10 5 0 0 5 -- 70 70 40 -- -- 25 25 -- 85 -- -- -- 10 5 0 0 10 -- 85 85 45 -- -- 30 30 -- ns ns ns ns ns ns ns ns ns
2 2 1, 2 1, 2
Notes: 1. t CHZ and tOHZ defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested.
7
HM62256B Series
Read Timing Waveform (1) (WE=VIH)
t RC
Address
Valid address t AA t ACS
CS t OH t OE t OLZ OE t OHZ t CHZ Dout High impedance Valid data
Read Timing Waveform (2) (WE=VIH, CS=VIL , OE=VIL )
t RC Address tAA t OH Dout Valid data Valid address t OH
8
HM62256B Series
Read Timing Waveform (3) (WE=VIH, OE=VIL )*1
t ACS CS t CLZ High impedance
t CHZ Valid data
Dout
Note: 1. Address must be valid prior to or simultaneously with CS going low.
9
HM62256B Series
Write Cycle
HM62256B -4 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time WE to output in high-Z Data to write time overlap Data hold from write time Output active from end of write -5 -7 -8
Symbol Min Max Min Max Min Max Min Max Unit Notes t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW 45 35 0 35 30 0 0 20 0 5 0 -- -- -- -- -- -- 20 -- -- -- 20 55 40 0 40 35 0 0 25 0 5 0 -- -- -- -- -- -- 20 -- -- -- 20 70 60 0 60 50 0 0 30 0 5 0 -- -- -- -- -- -- 25 -- -- -- 25 85 75 0 75 55 0 0 35 0 5 0 -- -- -- -- -- -- 40 -- -- -- 40 ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 7 3, 8 6 1, 2, 7 4 5
Output disable to output in high-Z t OHZ
Notes: 1. t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 4. t CW is measured from CS going low to the end of write. 5. t AS is measured from the address valid to the beginning of write. 6. t WR is measured from the earlier of WE or CS going high to the end of write cycle. 7. Durng this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention, tWP tWHZ max + tDW min.
10
HM62256B Series
Write Timing Waveform (1) (OE Clock)
t WC Address
Valid address t AW t WR
OE t CW CS
*1
t AS
t WP
WE t OHZ Dout High impedance t DW Din High impedance t DH
Valid data
Note: 1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state.
11
HM62256B Series
Write Timing Waveform (2) (OE Low Fixed) (OE = VIL )
t WC Address
Valid address t CW t WR
CS
*1
t AW tWP WE tAS t WHZ Dout t DW Din High impedance t DH
*4
t OH
t OW
*2
*3
Valid data
Notes: 1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. 2. Dout is the same phase of the write data of this write cycle. 3. Dout is the read data of next address. 4. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the output must not be applied to them.
12
HM62256B Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
Parameter VCC for data retention Data retention current Symbol VDR I CCDR Min 2.0 -- -- -- Chip deselect to data retention time t CDR Operation recovery time Notes: 1. 2. 3. 4. 5. 6. tR 0 t RC
*5
Typ*1 -- 0.05 0.05 0.05 -- --
Max 5.5 30*2 10 3
*4 *3
Unit V A
Test Conditions*6 CS V CC -0.2 V, Vin 0 V VCC = 3.0 V, Vin 0 V CS V CC -0.2 V,
-- --
ns ns
See retention waveform
Typical values are at VCC = 3.0 V, Ta = 25C and not guaranteed. 10 A max at Ta = 0 to + 40C. This characteristics guaranteed for only L-SL version. 3 A max at Ta = 0 to +40C. This characteristics guaranteed for only L-UL version. 0.6 A max at Ta = 0 to +40C. t RC = read cycle time. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention mode, other input levels (address, WE, OE, I/O) can be in the high impedance state.
Low V CC Data Retention Timing Waveform
Data retention mode VCC 4.5V t CDR 2.2V VDR CS 0V CS > VCC - 0.2V tR
13
HM62256B Series
Package Dimensions
HM62256BLP Series (DP-28)
35.60 36.50 Max
Unit: mm
28
15 13.40 14.60 Max
1 1.90 Max
1.20
14 2.54 Min 5.70 Max 15.24
0.51 Min
0.25 - 0.05 0 - 15
+ 0.11
2.54 0.25
0.48 0.10
HM62256BLSP Series (DP-28NA)
36.0 28 37.32 Max 15
7.37 Max
Unit: mm
1
1.3
2.2 Max
14 5.08 Max
7.1
7.62
0.51 Min
2.54 Min
0.25 - 0.05 0 - 15
+ 0.11
2.54 0.25
0.48 0.10
14
HM62256B Series
HM62256BLFP Series (FP-28DA)
18.00 18.75 Max 28 15 8.40
Unit: mm
1 1.27 Max
14
3.00 Max
+ 0.08 - 0.07
11.80 0.30 1.70 0 - 10
1.27 0.10
0.40 - 0.05
0.20 0.10
+ 0.10
0.17
1.00 0.20
HM62256BLT Series (TFP-32DA)
8.00 8.20 Max 32 17
Unit: mm
1
16 0.50
0.20 0.10
0.08 M 14.00 0.20 0.80 0-5 0.50 0.10
0.45 Max 0.17 0.05 1.20 Max
12.40
0.10
0.13 0.05
15

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